#Computer fundamental notes in hindi software

Data Memory Access speeds up memory operations and data transfer.

It contains two 16-bit registers, one is DMA Address Register and the other one is Terminal Count Register. In 8257 DMA Controller, the highest priority channel is acknowledged. 8257 DMA ControllerĨ257 DMA Controller is a type of DMA Controller, that when a single Intel 8212 I/O device is paired with it, becomes 4 channel DMA Controller. Each channel in the 8237 DMA Controller has to be programmed separately. In these present channels, the channel has to be given the highest priority to be decided by the Priority Encoder.

Transparent Mode: Transparent Mode in DMA does not require any bus in the transfer of the data as it works when the CPU is executing the transaction.Ĩ237 DMA Controller is a type of DMA Controller which has a flexible number of channels but generally works on 4 Input-Output channels.

It works more easily for higher-priority tasks. Continuous request for bus control is generated by this Data Transfer Mode.

Cycle Stealing Mode: In Cycle Stealing Mode, buses are handed over to the CPU by the DMA after the transfer of each byte.

Burst Mode: In Burst Mode, buses are handed over to the CPU by the DMA if the whole data is completely transferred, not before that.

There are 3 modes of data transfer in DMA that are described below.

Control to define the mode of transfer such as read or write.It also sends word count which is the number of words in the memory block to be read or written.The starting address of the memory block where the data is available (to read) or where data are to be stored (to write).When BG (bus grant) input is 1, the CPU has relinquished the buses and DMA can communicate directly with the memory.Įxplanation: The CPU initializes the DMA by sending the given information through the data bus. When BG (bus grant) input is 0, the CPU can communicate with DMA registers. Through the use of the address bus and allowing the DMA and RS register to select inputs, the register within the DMA is chosen by the CPU. The unit communicates with the CPU through the data bus and control lines. The figure below shows the block diagram of the DMA controller. Therefore, the CPU can both read and write into the DMA registers under program control via the data bus. Note: All registers in the DMA appear to the CPU as I/O interface registers. Control register – It specifies the transfer mode.Word count register – It contains the number of words to be transferred.

Address register – It contains the address to specify the desired location in memory.The DMA controller registers have three registers as follows. Interleaved DMA: Interleaved DMA are those DMA that read from one memory address and write from another memory address.

#Computer fundamental notes in hindi software

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